數(shù)字集成電路分析與設計：深亞微米技術

定　價：￥58.00

作　者：	美David A.Hodges等著
出版社：	清華大學出版社
叢編項：	國外大學優(yōu)秀教材微電子類系列
標　簽：	集成電路

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ISBN：	9787302090618	出版時間：	2004-08-01	包裝：	平裝
開本：	24cm	頁數(shù)：	546	字數(shù)：

內(nèi)容簡介

　　本書的第3版，把當前數(shù)字集成電路中已無可爭議地占絕對主導地位的CMOS電路技術作為主要內(nèi)容。全書以當前工業(yè)界領先的0.18T微米和0.13微米的工藝技術為基礎，注入了許多深亞微米領域電路設計方面的資料，如最先進的電路制造工藝、BSIM3短溝器件模型、深亞微米的互連技術和時鐘技術、基于邏輯力度（Logic Effort）的高速CMOS電路設計技術、電源網(wǎng)絡設計等。此外，第3版還新增了一些較新和較深的內(nèi)容，如快閃存儲器（Flash Memory）、鐵電存儲器（FRAM）、鎖相環(huán)（PLL）等，因此第3版明顯地具有集成電路深亞微米時代的特點。本書可用作高等院校電子信息、自動控制、電氣工程、精密儀器等專業(yè)本科高年級演密儀器等專業(yè)本科高年級和研究生有關集成電路課程的教材。全書共分11章，其中第1-8章為最基本的內(nèi)容，第9-11章可根據(jù)不同的教學計劃和教學要求選擇不同的內(nèi)容。本書各章中內(nèi)容較深的部分可供講授研究生課程時選用。由于本書內(nèi)容選進詳實，因此對于從事集成電路設計的工程技術人員來說也是一本不可多得的優(yōu)秀參考書。

作者簡介

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圖書目錄

1  DeepSubmicron Digital IC Design
  1.1  Introduction
  1.2  Brief History of IC Industry
  1.3  Review of Digital Logic Gate Design
  1.3.1  Basic Logic Functions
  1.3.2  Implementation of Logic Circuits
  1.3.3  Definition of Noise Margin
  1.3.4  Definition of Transient Characteristics
  1.3.5  Power Estimation
  1.4  Digital Integrated Circuit Design
  1.4.1  MOS Transistor Structure and Operation
  1.4.2  CMOS Versus NMOS
  1.4.3  Deep Submicron Interconnect
  1.5  Computer-Aided Design of Digital Circuits
  1.5.1  Circuit Simulation and Analysis
  *1.6  The ChallengesAhead
  1.7  Summary
2  MOS Transistors
  2.1  Introduction
  2.2  Structure and Operation of the MOS Transistor
  2.3  Threshold Voltage of the MOS Transistor
  2.4  First-Order Current-Voltage Characteristics
  2.5  Derivation of Velocity-Saturated Current Equations
  2.5.1  Effect of High Fields
  2.5.2  Current Equations for Velocity-Saturated Devices
  *2.6  Alpha-Power Law Model
  2.7  Subthreshold Conduction
2.8  Capacitances of the MOS Transistor
  2.8.1  Thin-Oxide Capacitance
  2.8.2  pn Junction Capacitance
  2.8.3  Overlap Capacitance
2.9  Summary
Fabrication, Layout, and Simulation
3.1  Introduction
3.2  IC Fabrication Technology
  3.2.1  Overview of IC Fabrication Process
  3.2.2  IC Photolithographic Process
  3.2.3  Making Transistors
  3.2.4  Making Wires
  3.2.5  Wire Capacitance and Resistance
3.3  Layout Basics
3.4  Modeling the MOS Transistor for Circuit Simulation
  3.4.1  MOS Models in SPICE
  3.4.2  Specifying MOS Transistors
3.5  SPICE MOS LEVEL i Device Model
  3.5.1  Extraction of Parameters for MOS LEVEL 1
*3.6  BSIM3 Model
  3.6.1  Binning Process in BSIM3
  3.6.2  Short-Channel Threshold Voltage
  3.6.3  Mobility Model
  3.6.4  Linear and Saturation Regions
  3.6.5  Subthreshold Current
  3.6.6  Capacitance Models
  3.6.7  Source/Drain Resistance
*3.7  Additional Effects in MOS Transistors
  3.7.1  Para'meter Variations in Production
  3.7.2  Temperature Effects
  3.7.3  Supply Variations
  3.7.4  Voltage Limitations
  3.7.5  CMOS Latch-up
*3.8  Silicon-on-Insulator (SOI) Technology
*3.9  SPICE Model Summary
MOS Inverter Circuits
4.1 Introduction
4.2  Voltage Transfer Characteristics
4.3  Noise Margin Definitions
  4.3.1  Single-Source Noise Margin (SSNM)
  4.3.2  Multiple-Source Noise Margin (MSNM)
4.4  Resistive-Load Inverter Design
  4.5  NMOS Transistors as Load Devices
  4.5.1  Saturated Enhancement Load
  4.5.2  Linear Enhancement Load
  4.6  Complementary MOS (CMOS) Inverters
  4.6.1  DC Analysis of CMOS Inverter
  4.6.2 Layout Design of CMOS Inverter
  4.7  Pseudo-NMos Inverters
  4.8  Sizing Inverters
  4.9  Tristate Inverters
  4.10  Summary
5  Static MOS Gate Circuits
  5.1  Introduction
  5.2  CMOS Gate Circuits
  5.2.1  Basic CMOS Gate Sizing
  5.2.2  Fanin and Fanout Considerations
  5.2.3  Voltage Transfer Characteristics (VTC)
  of CMOS Gates
  5.3  Complex CMOS Gates
  5.4  XOR and XNOR Gates
  5.5  Multiplexer Circuits
  5.6  Flip-Flops and Latches
  5.6.1  Basic Bistable Circuit
  5.6.2  SR Latch
  5.6.3  JK Flip-Flop
  5.6.4  JK Master-Slave Flip-Flop
  5.6.5  JK Edge-Triggered Flip-Flop
  5.7  D Flip-Flops and Latches
  5.8  Power Dissipationin CMOS Gates
  5.8.1  Dynamic (Switching) Power
  5.8.2  Static (Standby) Power
  5.8.3  Complete Power Equation
  5.9  Power and Delay Tradeoffs
  5.10  Summary
6  High-Speed CMOS Logic Design
  6.1  Introduction
  6.2  Switching Time Analysis
  6.2.1  Gate Sizing Revisited--Velocity Saturation Effects
  6.3  Detailed Load Capacitance Calculation
  6.3.1  Fanout Gate Capacitance
  6.3.2  Self-Capacitance Calculation
  6.3.3  Wire Capacitance
  6.4  Improving Delay Calculation with Input Slope
  6.5  Gate Sizing for Optimal Path Delay
  6.5.1  Optimal Delay Problem
  6.5.2  Inverter Chain Delay Optimization--FO4 Delay
  6.5.3  Optimizing Paths with NANDs and NORs
  6.6  Optimizing Paths with Logical Effort
  6.6.1  Derivation of Logical Effort
  6.6.2  Understanding Logical Effort
  6.6.3  Branching Effort and Sideloads
  6.7  Summary
  Transfer Gate and Dynamic Logic Design
  7.1  Introduction
  7.2  Basic Concepts
  7.2.1  Pass Transistors
  7.2.2  Capacitive Feedthrough
  7.2.3  Charge Sharing
  7.2.4  Other Sources of Charge Loss
  7.3  CMOS Transmission Gate Logic
  7.3.1  Multiplexers Using CMOS Transfer Gates
  7.3.2  CMOS Transmission Gate Delays
  7.3.3  Logical Effort with CMOS Transmission Gates
  7.4  Dynamic D-Latches and D Flip-Flops
  7.5  Domino Logic
  7.5.1  Logical Effort for Domino Gates
  7.5.2  Limitations of Domino Logic
  7.5.3  Dual-Rail (Differential) Domino Logic
  7.5.4  Self-Resetting Circuits
  7.6  Summary
8  Semiconductor Memory Design
  8.1  Introduction
  8.1.1  Memory Organization
  8.1.2  Types of Memory
  8,1.3  Memory Timing Parameters
  8.2  MOS Decoders
  8.3  Static RAM Cell Design
  8.3.1  Static Memory Operation
  8.3.2  Read Operation
  8.3.3  Write Operation
  8.3.4  SRAM Cell Layout
  8.4  SRAM Column I/O Circuitry
  8.4.1  Column Pull-Ups
  8.4.2  Column Selection
  8.4.3  Write Circuitry
  8.4.4  Read Circuitry
  8.5  Memory Architecture
  8.6  Summary
9  AdditionaITopics in Memory Design
  9.1  Introduction
  *9.2  Content-Addressable Memories (CAMs)
  *9.3  Field-Programmable Gate Array
  9.4  Dynamic Read-Write Memories
  9.4.1  Three-Transistor Dynamic Cell
  9.4.2  One-Transistor Dynamic Cell
  9.4.3  External Characteristics of Dynamic RAMs
  9.5  Read-Only Memories
  9.5.1  MOS ROM Cell Arrays
  9.6  EPROMs and E2pROMs
  *9.7  Flash Memory
  *9.8  FRAMs
  9.9  Summary'
10 Interconnect Design
  10.1  Introduction
  10.2  Interconnect RC Delays
  10.2.1  Wire Resistance
  10.2.2  Elmore Delay Calculation
  10.2.3  RC Delay in Long Wires
  10.3  Buffer Insertion for Very Long Wires
  10.4  Interconnect Coupling Capacitance
  10.4.1  Components of Coupling Capacitance
  10.4.2  Coupling Effects on Delay
  10.4.3  Capacitive Noise or Crosstalk
  *10.5  Interconnect Inductance
  * 10.6  Antenna Effects
  10.7  Summary
11 Power Grid and Clock Design
  11.1  Introduction
  11.2  Power Distribution Design
  11.2.1  IR Drop and Ldi/ dt
  11.2.2  Electromigration
  11.2.3  Power Routing Considerations
  11.2.4  Decoupling Capacitance Design
  11.2.5  Power Distribution Design Example
  11.3  Clocking and Timing Issues
  11.3.1  Clock Definitions and Metrics
  11.3.2  Clock Skew
  11.3.3  Effect of Noise on Clocks and FFs
  11.3.4  Power Dissipation in Clocks
  11.3.5  Clock Generation
  11.3.6  Clock Distribution for High-Performance Designs
  11.3.7  Example of a Clock Distribution Network
  11.4  Phase-Locked Loops/Delay-Locked Loops
  11.4.1  PLL Design Considerations
  l1.4.2  Clock Distribution Summary
Index