VHDL入門與應(yīng)用

第1章 緒論                  
 1.1 EDA工具的歷史及現(xiàn)狀                  
 1.2 硬件描述語言HDL                  
 1.3 VHDL簡述                  
 1.3.1 VHDL的誕生                  
 1.3.2 VHDL語言特點(diǎn)                  
 1.3.3 VHDL設(shè)計(jì)簡述                  
 1.3.4 VHDL的結(jié)構(gòu)體描述                  
 1.4 一個(gè)簡單實(shí)例                  
 1.5 小結(jié)                  
 第2章 VHDL語言基礎(chǔ)                  
 2.1 VHDL程序設(shè)計(jì)基本結(jié)構(gòu)                  
 2.1.1 實(shí)體聲明                  
 2.1.2 結(jié)構(gòu)體                  
 2.1.3 配置                  
 2.1.4 程序包                  
 2.2 VHDL中的數(shù)據(jù)                  
 2.2.1 標(biāo)志符                  
 2.2.2 數(shù)據(jù)對(duì)象                  
 2.2.3 VHDL數(shù)據(jù)類型                  
 2.2.4 用戶自定義類型                  
 2.2.5 類型聲明與子類型聲明的地方                  
 2.3 VHDL中的表達(dá)式                  
 2.3.1 操作符                  
 2.3.2 操作數(shù)                  
 2.4 小結(jié)                  
 第3章 VHDL中的描述語句                  
 3.1 順序描述語句                  
 3.1.1 對(duì)象與賦值語句                  
 3.1.2 變量賦值與信號(hào)賦值                  
 3.1.3 if語句                  
 3.1.4 case語句                  
 3.1.5 loop語句                  
 3.1.6 子程序                  
 3.1.7 return語句                  
 3.1.8 wait語句                  
 3.1.9 null語句                  
 3.2 并行描述語句                  
 3.2.1 進(jìn)程語句                  
 3.2.2 塊語句                  
 3.2.3 順序描述語句的并行版本                  
 3.2.4 組件例化語句                  
 3.2.5 生成語句                  
 3.3 子程序                  
 3.3.1 子程序聲明                  
 3.3.2 子程序主體                  
 3.3.3 子程序重載                  
 3.3.4 決斷函數(shù)                  
 3.4 小結(jié)                  
 第4章 編程實(shí)例                  
 4.1 編碼器                  
 4.2 譯碼器                  
 4.3 加法器                  
 4.4 寄存器                  
 4.5 移位寄存器                  
 4.6 計(jì)數(shù)器                  
 4.7 串并轉(zhuǎn)換器                  
 4.8 并串轉(zhuǎn)換器                  
 4.9 存儲(chǔ)器的實(shí)現(xiàn)和應(yīng)用                  
 4.10 信號(hào)發(fā)生器                  
 4.11 更為復(fù)雜的信號(hào)發(fā)生器                  
 4.12 序列計(jì)數(shù)器                  
 4.13 一個(gè)具有層次化的設(shè)計(jì)示例----微處理器                  
 4.13.1 AM2901結(jié)構(gòu)簡介                  
 4.13.2 為AM2901建立一個(gè)程序包                  
 4.13.3 AM2901功能設(shè)計(jì)                  
 4.13.4 AM2901頂層數(shù)據(jù)包                  
 4.13.5 AM2901頂層實(shí)體                  
 4.14 小結(jié)                  
 第5章 MAX+plusⅡ及其應(yīng)用                  
 5.1 MAX+plusⅡ簡介與應(yīng)用例解                  
 5.2 安裝MAX+plusⅡ 9.4                  
 5.3 啟動(dòng)MAX+plusⅡ                  
 5.4 感性認(rèn)識(shí)----編寫一個(gè)計(jì)數(shù)器counter                  
 5.4.1 建立VHDL語言的設(shè)計(jì)輸入文件                  
 5.4.2 建立工程                  
 5.4.3 設(shè)置編譯選項(xiàng), 編譯綜合工程                  
 5.4.4 仿真                  
 5.4.5 器件編程                  
 5.5 利用Altera公司的庫快速生成程序                  
 5.6 小結(jié)                  
 第6章 Quartus及其應(yīng)用                  
 6.1 Quartus 2000.02 版軟件包                  
 6.2 安裝Quartus 2000.02                  
 6.3 感性認(rèn)識(shí)----編寫一個(gè)除法小程序                  
 6.3.1 使用向?qū)Ы⒐こ蘢ivide                  
 6.3.2 建立設(shè)計(jì)輸入文件divider.vhd                  
 6.3.3 設(shè)定編譯選項(xiàng)                  
 6.3.4 編譯文件                  
 6.3.5 編輯波形仿真文件                  
 6.3.6 進(jìn)行仿真并分析結(jié)果                  
 6.4 除法器電路的一些改進(jìn)                  
 6.5 Quartus中Altera庫函數(shù)                  
 6.5.1 直接調(diào)用方式                  
 6.5.2 使用Quartus的Megawizard Plus_In Manager                  
 6.6 小結(jié)                  
 第7章 VHDL編程指南                  
 7.1 一些相關(guān)設(shè)計(jì)理論                  
 7.1.1 使用自頂向下的系統(tǒng)級(jí)設(shè)計(jì)方法                  
 7.1.2 使用狀態(tài)機(jī)的設(shè)計(jì)方法                  
 7.1.3 使用流水線的設(shè)計(jì)方法                  
 7.2 設(shè)計(jì)中的一些重要概念                  
 7.2.1 組合邏輯和時(shí)序邏輯                  
 7.2.2 Latch和Flip_flop                  
 7.2.3 資源庫的使用                  
 7.2.4 片內(nèi)存儲(chǔ)器RAM的使用                  
 7.2.5 高阻狀態(tài)設(shè)置                  
 7.3 可編程邏輯器件CPLD和FPGA                  
 7.3.1 CPLD簡介                  
 7.3.2 FPGA簡介                  
 7.4 小結(jié)                  
 附錄A VHDL保留字                  
 附錄B 部分FPGA廠家名錄                  
 附錄C EDA工具軟件一覽表                  
 C.1 VHDL編輯軟件一覽表                  
 C.2 RTL級(jí)綜合工具軟件一覽表                  
 C.3 VHDL仿真工具軟件一覽表                  
 C.4 FPGA編程軟件一覽表                  
 附錄D 預(yù)定義的程序包                  
 D.1 std_logic_1164程序包                  
 D.2 std_logic_arith程序包                  
 D.3 std_logic_unsigned程序包                  
 D.4 std_logic_signed程序包                  
 附錄E VHDL語法的BNF范式表示                  
 參考文獻(xiàn)                  
 后 記